Inverter apparatus

ABSTRACT

A CPU calculates, based on a frequency command value for driving a motor and on a state quantity of the motor, an output-voltage command value in which only the phase advances while amplitude is constant in each calculation period, without reducing the calculation period. An ASIC reflects the output-voltage command value in a triangular wave signal in a time-series order to compare with each other, and outputs a PWM signal to a switching circuit. Thus, a waveform of an output voltage is made close to a sine wave irrespective of an output frequency being high or low, and a processing load of the CPU is reduced.

TECHNICAL FIELD

The present invention relates to an inverter device for driving a motorat an arbitrary frequency.

BACKGROUND ART

An inverter device for driving a motor such as an induction motor and asynchronous motor generally includes an output-voltage calculating unitthat calculates an output voltage command in each calculation period,based on a frequency command value input to drive a motor and a statequantity of the motor detected; a PWM-pattern generating unit thatoutputs a PWM (pulse-width modulation) signal based on a comparisonbetween an output-voltage command value output by the output-voltagecalculating unit and a triangular wave signal; and a switching unit thatswitches a direct voltage according to the PWM signal output by thePWM-pattern generating unit and supplies an alternating voltage with apredetermined frequency to the motor. However, the waveform of thealternating voltage output by the switching unit becomes a staircasepattern, and hence, for the purpose of reducing current ripple or thelike, various devices are proposed so as to allow the waveform of anoutput voltage to approach a sine wave as close as possible.

For example, Patent document 1 discloses a technology of obtaining asmooth output voltage by dividing a difference ΔV, between anoutput-voltage command value V1 calculated in one calculation period andan output-voltage command value V2 calculated in the next onecalculation period, by the number N of vertices of a triangular wavesignal included in one calculation period, and by linearly complementingand changing an amplitude value of each of the output-voltage commandvalues, by ΔV/N each, at each vertex of the triangular wave signalincluded in the calculation period, to thereby change the output-voltagecommand value from a staircase pattern to a linear pattern.

The above Patent document 1 is as follows.

Patent document 1: Japanese Patent Application Laid-Open No. H6-22556

In the above technology described in Patent document 1, however, a codeindicating a direction of voltage change in one calculation period isfixed. Therefore, as shown in FIG. 1, if the direction of voltage changeis reversed in the middle of the one calculation period, anoutput-voltage command value indicating such a change cannot beobtained. This case is specifically explained with reference to FIG. 1.FIG. 1 is a diagram of the comparison between a changing waveform of anoutput voltage command that is desired to actually output and a changingwaveform of an output voltage command that is actually output.

FIG. 1(1) illustrates a correlation between a changing waveform 1 of theoutput voltage command that is desired to actually output and atriangular wave signal 2 in one calculation period. FIG. 1(2)illustrates a correlation between a changing waveform 3 of the outputvoltage command that is actually output and the triangular wave signal 2in one calculation period. As shown in FIG. 1, an amplitude value of theoutput voltage command in one calculation period is changing by eachΔV/N at each vertex of the triangular wave signal 2.

When vertices (e.g., a maximum value point on the positive side) of thesine wave are included in one calculation period as shown in FIG. 1(1),the changing waveform 1 of the output voltage command, which is actuallydesired to be output, becomes a staircase waveform in which an upwardstaircase is followed by a downward staircase portion 4 in the onecalculation period. On the contrary, in the technology described in thePatent document 1, because the direction of voltage change is onedirection in the one calculation period as shown in FIG. 1(2), thechanging waveform 2 of the output voltage command, which is actuallyoutput, is only an upward staircase pattern. Therefore, the changingwaveform 2 becomes a waveform of the upward staircase in an area 5corresponding to the downward staircase portion 4 in the changingwaveform 1 of the output voltage command, which is actually desired tobe output as shown in FIG. 1(1).

To avoid this pattern, an area divided by a dotted line needs to bereduced by one portion so that the downward staircase portion 4 of FIG.1(1) is included in the next calculation period, namely, the calculationperiod is shortened. Alternatively, the calculation period needs tocoincide with the phase of the sine wave by shifting the phase of thesine wave to the right as the whole. To implement this, in the formercase, a CPU that calculates an output voltage command needs to beupgraded, which causes an increase in cost. In the latter case, theprocessing load increases.

FIG. 2 is a diagram of the comparison between an output voltage waveformand a sine waveform. FIG. 2 illustrates a waveform of an output voltage8 when ¼ cycle of a sine wave 7 is set to one calculation period. Asshown in FIG. 2, a voltage between calculation periods is obtained bylinear complement. Therefore, the output voltage 8 is output as avoltage that linearly changes between calculation periods. At this time,if an output frequency is low, the calculation period with respect tothe cycle of the sine wave becomes sufficiently short, which allows thesine wave to be divided into fine intervals. Therefore, deviation fromthe sine wave is small even by the linear complement, but if the outputfrequency is high, the calculation period becomes comparatively long.Therefore, in the conventional technology, it becomes difficult toapproximate a fine curve of the sine wave, which causes the deviationfrom the sine wave to become significant.

The present invention has been achieved in view of the above problems,and it is an object of the present invention to obtain an inverterdevice capable of approaching the waveform of an output voltage closerto a sine wave irrespective of whether output frequency is high or low,as compared with the conventional technology, and of reducing theprocessing load of a CPU that calculates an output voltage command.

DISCLOSURE OF INVENTION

In the present invention, an inverter device includes an output-voltagecalculating unit that calculates an output voltage command based on afrequency command value for driving a motor and a state quantity of themotor, in each calculation period; a PWM-pattern generating unit thatoutputs a PWM signal according to an output-voltage command value outputby the output-voltage calculating unit; and a switching unit thatswitches a direct voltage according to the PWM signal output by thePWM-pattern generating unit and supplies an alternating voltage with apredetermined frequency to the induction motor. The output-voltagecalculating unit includes a function of calculating a plurality ofoutput-voltage command values in which amplitudes are the same as eachother but only phase advances under a fixed condition, in eachcalculation period.

According to the present invention, the output-voltage command value inwhich only the phase advances is updated a plurality of times within acalculation period. Therefore, even if there are a small number ofcalculation periods in the cycle of a fundamental wave of an outputvoltage, it is possible to obtain an output voltage with a waveformcloser to the sine wave. Therefore, the current ripple is reduced moreas compared with the conventional technology, thus achieving torqueripple reduction and efficiency increase. Furthermore, a CPU thatcalculates the output voltage command only needs to add a function ofcalculating a plurality of output-voltage command values in which onlythe phase advances. Therefore, the processing load of the CPU can bereduced, thus, there is no need to use an expensive CPU.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram of the comparison between a changing waveform of anoutput voltage command that is actually desired to be output and achanging waveform of an output voltage command that is actually output;

FIG. 2 is a diagram of the comparison between an output voltage waveformand a sine waveform;

FIG. 3 is a block diagram of the configuration of an inverter deviceaccording to one embodiment of the present invention;

FIG. 4 is a flowchart for explaining the operation of an output voltagecalculator shown in FIG. 3;

FIG. 5 is a time chart for explaining a specific example of operationsfor generating a plurality of output voltage commands in one calculationperiod in the output voltage calculator shown in FIG. 3;

FIG. 6 is a time chart for explaining the operations of a PWM patterngenerator (ASIC) shown in FIG. 3; and

FIG. 7 is a waveform diagram of the comparison between an output voltageobtained by the inverter device shown in FIG. 3 and an output voltagebased on the conventional technology.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Exemplary embodiments of an inverter device according to the presentinvention are explained in detail with reference to the accompanyingdrawings.

FIG. 3 is a block diagram of the configuration of an inverter deviceaccording to one embodiment of the present invention. The inverterdevice of FIG. 3 includes an output voltage calculator 10, a PWM patterngenerator 11 that receives an output of the output voltage calculator10, and a switching circuit 12 that receives an output of the PWMpattern generator 11. The switching circuit 12 is connected with a motor(an induction motor or a synchronous motor) 13. The motor 13 is shownhere as a three-phase motor.

The output voltage calculator 10 includes a central processing unit(hereinafter, “CPU”) 14 that creates various types of data, and a datatransmitter 15 being an interface for transmitting the data created tothe PWM pattern generator 11.

To the CPU 14, a frequency command 16 for driving the motor 13 and astate quantity 17 of the motor 13 are input from the outside. The statequantity 17 includes a current value as a main value when the motor 13is an induction machine, and further includes a speed value added to themain value when the motor 13 is a synchronous machine. The current valueis detected by fixing a current detector (a current transformer and aresistor, etc.) to an electric wire. The speed value is detected byfixing an encoder to the rotary shaft of the motor 13. In thisspecification, the motor 13 is the induction machine and the statequantity 17 is the current value.

The CPU 14 loads the state quantity 17 of the motor 13 detected in eachcalculation period, and calculates an output voltage command (voltagedata) based on the state quantity 17. Further, the CPU 14 createstriangular-wave amplitude data for providing the cycle of a triangularwave signal being a carrier wave for obtaining a PWM signal, andreflection timing data for providing the number of vertices of atriangular wave signal for defining intervals of reflection.

At this time at which an output voltage command is to be calculated, theCPU 14 calculates a plurality of output-voltage command values in whichthe amplitudes are the same as each other but only the phase advances inthe calculation period under a fixed condition. In the embodiment, threeoutput-voltage command values are obtained as the output-voltage commandvalues.

As a result of this, the data (voltage data, triangular-wave amplitudedata, reflection timing data, etc.) created is transmitted from the datatransmitter 15 to the PWM pattern generator 11. A synchronization signalfor synchronization between the calculation period and the reflectiontiming is also transmitted thereto.

The PWM pattern generator 11 is implemented by ASIC being a dedicatedsemiconductor integrated circuit. An ASIC 11 includes a data receiver 21being an interface, a buffer A22, a buffer B23, a buffer C24, areflection timing register 25, a triangular wave counter 26, and acomparator 28.

The data receiver 21 loads the data (voltage data, triangular-waveamplitude data, reflection timing data, etc.) created in the CPU 14,outputs the voltage data to the buffer A22, the buffer B23, and thebuffer C24, respectively, to be temporarily stored. At this time, whenthere is one voltage data, the one voltage data is output to the threebuffer A22, the buffer B23, and the buffer C24. However, if there arethree voltage data, the three voltage data are output to the threebuffer A22, the buffer B23, and the buffer C24, respectively, in thetime-series order.

Furthermore, the data receiver 21 outputs the reflection timing dataloaded, to the reflection timing register 25, and outputs thetriangular-wave amplitude data to the triangular wave counter 26. Avoltage register 27 uses the reflection timing data stored in thereflection timing register 25. The triangular wave counter 26 incrementsor decrements the counter according to the triangular-wave amplitudedata to generate a triangular wave, and supplies the triangular wavecreated to the comparator 28.

The voltage register 27 loads the data stored in the buffer A22, thebuffer B23, and the buffer C24 in the time-series order based on thesynchronization signal and the reflection timing data, stores them for afixed period (period for a predetermined number of vertices of atriangular wave signal), respectively, and supplies the data to thecomparator 28.

The comparator 28 compares a value of the voltage register 27 with avalue of the triangular wave counter 26, and outputs a PWM command,being a pulse signal of which pulse width is changed, to the switchingcircuit 12.

The switching circuit 12 performs on-off operation according to the PWMcommand output by the PWM pattern generator (ASIC) 11 so that threeupper-arm switching elements and three lower-arm switching elements donot mutually overlap each other, creates a three-phase alternatingvoltage with a predetermined frequency from a direct voltage of +V, andsupplies the voltage to the motor 13.

The operation of the inverter device according to the embodiment isexplained below with reference to FIG. 3 through FIG. 7. An overallcalculation operation in the output voltage calculator is explainedfirst with reference to FIG. 4. FIG. 4 is a flowchart for explaining theoperation of the output voltage calculator shown in FIG. 3.

In FIG. 4, the CPU 14 decides a frequency of a triangular wave signal,being a carrier wave of a PWM signal, based on the frequency command 16received, and creates triangular-wave amplitude data (step ST1). Then,the CPU 14 executes processes at step ST2 to step ST12 in eachcalculation period of a predetermined time period AT, to obtain athree-phase alternating output-voltage command value V (Vu, Vv, Vw).

In other words, the CPU 14 detects a current value which is the statequantity 17 of the motor (step ST2), and converts current coordinates toa rotating orthogonal coordinate system in which d axis-q axis are setto two axes orthogonal to each other (step ST3). Then, the CPU 14calculates a phase θ in the sine wave in the calculation period from therotating coordinates (step ST4). Herein, in the embodiment, the phase θin one calculation period of the time period ΔT is divided into threeparts, such as a phase (hereinafter, “pre phase”) θ1 in a first timeperiod ΔT/3, a phase (hereinafter, “center phase”) θ2 in a second timeperiod ΔT/3, and a phase (hereinafter, “post phase”) θ3 in a third timeperiod ΔT/3, and each output-voltage command value in the respectivephases is obtained (see FIG. 5). Therefore, at step ST4, the CPU 14obtains the center phase θ2.

Then, the CPU 14 obtains a voltage Vd and a voltage Vq as direct current(step ST5), and determines whether there is any phase change (step ST6).In general, an amplitude value at time t of the sine wave that rotatesat an angular frequency ω is expressed by Asin ωt based on the amplitudeA, the angular frequency ω, and the time t, and the phase θ at this timeis ωt. Because the time t is an integration of time periods ΔT includingcalculation periods, the phase θ becomes θ=ωΣΔT. A phase change amountΔθ between calculation periods is Δθ=ωΔT. Therefore, at step ST6, anangular frequency ω of an output voltage is monitored to enabledetermination on the phase change amount, and it is possible todetermine in which phase of the sine wave the calculation period isincluded. It is noted that the phase θ is an integration of phase changeamounts ΔθO, i.e., θ=ΣΔθ.

For example, if the phase change amount is a predetermined value orless, it is determined that there is no phase change (step ST6, No). Inthis case, θ2=θ1=θ3, and hence, a voltage V2 in the center phase θ2 isobtained through voltage coordinate conversion (step ST7), and both avoltage V1 in the pre phase θ1 and a voltage V3 in the post phase θ3 areset to a value equal to the voltage V2 without calculation (step ST8),and the value is set to the output-voltage command value V (Vu, Vv, Vw)in the calculation period. The procedure at step ST1 to step ST4, stepST7, and step ST8 is a conventionally executed one.

However, in the conventional technology, because there is no idea thatthe phase in one calculation period is divided, the phase θ in thecalculation period is obtained at step ST4. Step ST8 is a procedurenewly generated when the phase in one calculation period is divided inthe embodiment. Therefore, in the embodiment, the process, which isadded when one output voltage command is calculated in one calculationperiod in the same manner as the conventional technology, is theprocedure executed at step ST8, and there is an extremely small amountof increase in the process.

On the other hand, if the phase change amount exceeds the predeterminedvalue, it is determined that there is any phase change (step ST6: Yes),and the CPU 14 obtains the pre phase θ1 and the post phase θ3,respectively (step ST9), and further obtains an output-voltage commandvalue V1 (Vu1, Vv1, Vw1) in the pre phase θ1, an output-voltage commandvalue V2 (Vu2, Vv2, Vw2) in the center phase θ2, and an output-voltagecommand value V3 (Vu3, Vv3, Vw3) in the post phase θ3, respectively,through voltage coordinate conversion (step ST10 to step ST12).

The operations at step ST4 and step ST9 to step ST12 are explained belowwith reference to FIG. 5. FIG. 5 is a time chart for explaining aspecific example of operations for generating a plurality of outputvoltage commands in one calculation period in the output voltagecalculator shown in FIG. 3. In FIG. 5, the vertical axis is phase θ andthe horizontal axis is time t.

In FIG. 5, there are shown two successive calculation periods 31 and 32with respect to an analog phase θana linearly rising from bottom left totop right at a certain angle, in a first-half cycle in a positive halfcycle of the sine wave. Each time period of calculation periods isexpressed by ΔT.

In the calculation period 31, the phase changes in the order of a prephase θ11 in a first time period ΔT/3, a center phase θ12 in a secondtime period ΔT/3, and a post phase θ13 in a third time period ΔT/3. Inthe calculation period 32, the phase changes in the order of a pre phaseθ21 in a first time period ΔT/3, a center phase θ22 in a second timeperiod θT/3, and a post phase θ23 in a third time period ΔT/3.

In each of the calculation period 31 and the calculation period 32,respective change amounts of the pre phase θ1 and the post phase θ3 withrespect to the center phase θ2 are equal to each other, which is Δθ/3. Aphase change amount (phase advance portion) Δθ between the calculationperiod 31 and the calculation period 32 is given as a difference betweenthe center phase θ12 and the center phase θ22, which is Δθ=ωΔT, asexplained above.

The calculation period 32 is explained below as one example. In theconventional technology, the phase θ obtained at step ST4 of FIG. 4 isthe center phase θ22, and this phase is the phase as the whole of onecalculation period. In the embodiment, however, the phase θ is dividedinto three parts and calculated. More specifically, the phases of thethree parts are obtained by first obtaining the center phase θ22 at stepST4 of FIG. 4 using the conventional technique, and then obtaining thepre phase θ21 when −ΔT/3 and the post phase θ23 when +ΔT/3, based on thecenter phase θ22 as a center, at step ST9 of FIG. 4.

The phase advance portion Δθ is obtained by a product ωΔT of the angularfrequency and the time period of the calculation period, as explainedabove. Therefore, if the output frequency does not change within thecalculation period, the pre phase θ21 and the post phase θ23 can becalculated, respectively, at step ST9 of FIG. 4, as follows:θ21=θ22−ωΔT/3=θ22−Δθ/3θ23=θ22+ωΔT/3=θ22+Δθ/3

At step ST10 to step ST12 of FIG. 4, three output-voltage command valuescorresponding to one calculation period of a time period ΔT arecalculated respectively using the three phases obtained in the abovemanner. This allows only the phase of each output voltage of theinverter in one calculation period of the time period ΔT to be changedby a time period of ΔT/3 each.

FIG. 6 is a time chart for explaining the operations of a PWM patterngenerator (ASIC) shown in FIG. 3. In FIG. 6, there are shown theoperations of the components in the ASIC 11 when the CPU 14 transmitsthe following data to the ASIC 11, such as a synchronization signal 41,three voltage data V11, V12, and V13, reflection timing 42, 43, and 44of each time period ΔT corresponding thereto, and data for a triangularwave signal 45, in the calculation period 31 shown in FIG. 5.

When the calculation process of the voltage data V11, V12, and V13 isfinished in the calculation period 31 of the time period ΔT, the CPU 14immediately performs a transmission process and quickly transmits thevoltage data V11, V12, and V13 together with other data to the ASIC 11,and allows the ASIC 11 to store them in the buffers. Thereafter, thesynchronization signal 41 is transmitted.

Therefore, as shown in FIG. 6, in the ASIC 11, in the calculation period31 of the time period ΔT, the voltage data V11 is first stored in thebuffer A22, the voltage data V12 is stored in the buffer B23, and then,the voltage data V13 is stored in the buffer C24.

The voltage register 27 fetches the voltage data V11 from the buffer A22in response to the synchronization signal 41, stores the data for a timeperiod Δt of the reflection timing 42, and then outputs the data. Whenthe time period Δt of the reflection timing 42 has elapsed, the voltageregister 27 fetches the voltage data V12 from the buffer B23, stores thedata for a time period Δt of the reflection timing 43, and then outputsthe data. Likewise, when the time period Δt of the reflection timing 43has elapsed, the voltage register 27 fetches the voltage data V13 fromthe buffer C24, stores the data for a time period Δt of the reflectiontiming 44, and then outputs the data.

The comparator 28 reflects the voltage data V11, V12, and V13respectively in the triangular wave signal 45 which is an output of thetriangular wave counter 26, in the respective time periods Δt of thereflection timing 42, 43, and 44, and outputs a PWM signal 46 to theswitching circuit 13. Herein, each time period Δt of the reflectiontiming 42, 43, and 44 indicates a period during which a predeterminednumber (three in the example of FIG. 6) of vertices of the triangularwave signal 45 has passed, and the start point and the end point thereofsynchronize to the vertices of the triangular wave signal 45.

In this manner, the three output-voltage command values calculated bythe CPU 14 within the time period ΔT of one calculation period areautomatically reflected at a timing specified by the CPU 14 in the ASIC11, and a PWM signal is created. The CPU 14 only specifies thereflection timing and does not perform reflection process, and hence,the processing load is reduced.

FIG. 7 is a waveform diagram of the comparison between an output voltageobtained in the inverter device shown in FIG. 3 and an output voltagebased on the conventional technology. FIG. 7(1) indicates a waveform ofthe output voltage obtained by the conventional technology. FIG. 7(2)indicates a waveform of the output voltage obtained by the embodiment.

As is clear from the explanation of the operations with reference toFIG. 4, in the conventional technology, one output-voltage command valueis obtained in each calculation period (time period ΔT). Therefore, whenthe output frequency becomes high and the calculation period becomerelatively long, the waveform of the output voltage becomes astaircase-shaped waveform in which the steps are significant, as shownin FIG. 7(1).

On the other hand, in the embodiment, in the calculation period (timeperiod ΔT) in which the phase change amount exceeds, for example, apredetermined value as shown in FIG. 7(2), only the phase is dividedinto three parts, and three output-voltage command values are obtainedone by one in each time period ΔT/3, such as V1 (θ1), V2 (θ3), and v3(θ3), and a PWM signal is generated for each value. Therefore, even ifthe output frequency becomes high and the calculation period becomesrelatively long, the steps in the staircase-shaped waveform can be madesmaller, which allows the waveform to approach a smoother sine wave.

The case where the phase is divided into three parts to obtain threeoutput voltage commands is explained for convenience in explanation.However, the number of output voltage commands capable of beingreflected per one calculation period can be selected if necessaryaccording to the throughput of the CPU 14 and the memory size of theASIC 11, and can also be changed arbitrarily according to need.

As explained above, in the embodiment, the output-voltage command valuein which only the phase advances is updated a plurality of times withina calculation period. Therefore, even if there are a small number ofcalculation periods in the cycle of a fundamental wave of an outputvoltage, it is possible to obtain an output voltage with a waveformcloser to the sine wave. Therefore, the current ripple is reduced moreas compared with the conventional technology, thus achieving torqueripple reduction and efficiency increase.

The CPU that calculates an output voltage command only needs to add thefunction of calculating a plurality of output-voltage command values inwhich only the phase advances. Thus, the increase in the calculationamount is comparatively small. In addition, the operation for updatingthe output-voltage command value a plurality of times is performed inthe ASIC 11, which is a semiconductor integrated circuit, withoutperformance of processes in the CPU. This allows reduction in theprocessing load of the CPU, and in addition to this, the calculationperiod is not reduced, and hence, there is no need to use an expensiveCPU.

The explanation made so far indicates the case where the phase isdivided into a plurality of parts in a calculation period in which aphase change amount exceeds the predetermined value, but if the cycle ofan output voltage is sufficiently large with respect to the calculationperiod, that is, if the output frequency is low, a large number ofcalculation periods are included in one cycle of the fundamental wave ofan output voltage, and a plurality of output-voltage command values arecalculated. Thus, a waveform satisfactorily close to the sine wave canbe obtained without outputting a voltage in which a plurality of phasesadvance in one period of the calculation period.

At step ST6 of FIG. 4, therefore, it is not determined whether the phaseis changed, but it is determined whether a frequency command value inputto drive the motor is smaller or greater than a predetermined value. Ifthe frequency command value is greater than the predetermined value, alarger number of output-voltage command values than the case where it issmaller than the predetermined value are calculated. Alternatively, ifthe frequency command value is greater than the predetermined value, aplurality of output-voltage command values may be calculated, and if itis smaller than the predetermined value, one output-voltage commandvalue may be calculated in the same manner as the conventionaltechnology.

As the latter example, for example, if it is sufficient that thecalculation period is 500 μseconds and 18 voltage changes are obtainedin one calculation period of output voltage, at step ST6, the processfor negative (No) is performed so as not to divide the phase into aplurality of parts in an area of an output frequency of1/(500μ×8)=111.11 Hz or less. And if the area of the output frequency ismore than that, a smaller number of calculation periods are included inone cycle of the fundamental wave of the output voltage. Therefore, toallow update of the voltage to be more quickly performed, the processfor positive (Yes) is performed so as to divide the phase into aplurality of parts and calculate the parts, to thereby increase thenumber of outputs of the output voltage commands in the calculationperiod.

According to this, the calculation load in a low-speed area can bereduced. Furthermore, a time for calculation only when the outputfrequency is low can be ensured. The calculation includes, for example,an error correction of an output voltage due to a time for prevention ofupper and lower arm short-circuit of the switching circuit.

In the embodiment, there is shown the configuration in which thereflection timing data indicating the number of vertices of thetriangular wave signal is included in data exchanged between the CPU andthe ASIC, and update timing of the output voltage command can be set ineach case, so as to enable handling even a case where automatic updateneeds to be performed and the calculation period needs to be switched.However, the present invention is not limited by the case, but variousmodifications are possible.

For example, (1) When timing of automatic reflection is fixed becausethe calculation period is fixed, a value may be set using hardware bysetting ports of the ASIC. (2) The ASIC receives the cycle of atriangular wave signal from the CPU to enable a user to change the cycleof the triangular wave signal, but if the cycle of the triangular wavesignal is fixed, there is no need to receive the cycle of the triangularwave signal from the CPU. Accordingly, the CPU does not also need toobtain the cycle of the triangular wave signal. (3) There is shown thecase where the reflection timing of the output voltage command in thetriangular wave signal is controlled by the number of vertices of thetriangular wave signal, but the reflection timing may be set in timebase. (4) Furthermore, the synchronization signal is used for a timingsignal to synchronize the vertices of the triangular wave signal and thecalculation timing of the CPU, but there may be a method ofimplementation in which the synchronization is not needed.

INDUSTRIAL APPLICABILITY

The present invention is suitable as an inverter device that obtains analternating voltage with an arbitrary frequency for driving a motor in awaveform more closer to a sine wave, that is, an inverter device thatobtains an alternating voltage with less current ripple and capable ofreducing torque ripple. between calculation periods. At this time, if anoutput frequency is low, the calculation period with respect to thecycle of the sine wave becomes sufficiently short, which allows the sinewave to be divided into fine intervals. Therefore, deviation from thesine wave is small even by the linear complement, but if the outputfrequency is high, the calculation period becomes comparatively long.Therefore, in the conventional technology, it becomes difficult toapproximate a fine curve of the sine wave, which causes the deviationfrom the sine wave to become significant.

The present invention has been achieved in view of the above problems,and it is an object of the present invention to obtain an inverterdevice capable of approaching the waveform of an output voltage closerto a sine wave irrespective of whether output frequency is high or low,as compared with the conventional technology, and of reducing theprocessing load of a CPU that calculates an output voltage command.

DISCLOSURE OF INVENTION

In the present invention, an inverter device includes an output-voltagecalculating unit that calculates a plurality of output voltage commandvalues in which amplitudes are the same as each other but only phaseadvances under a fixed condition, based on a frequency command value fordriving a motor and a state quantity of the motor, in each calculationperiod; a PWM-pattern generating unit that is a semiconductor integratedcircuit that includes a unit that temporarily stores each of theplurality of output-voltage command values output by the output-voltagecalculating unit; a unit that reflects the plurality of output-voltagecommand values stored, in a triangular wave signal in time-series order;and a unit that outputs a PWM signal based on the result of thereflection; and a switching unit that switches a direct voltageaccording to the PWM signal output by the PWM-pattern generating unitand supplies an alternating voltage with a predetermined frequency tothe induction motor.

According to the present invention, the output-voltage command value inwhich only the phase advances is updated a plurality of times within acalculation period. Therefore, even if there are a small number ofcalculation periods in the cycle of a fundamental wave of an outputvoltage, it is possible to obtain an output voltage with a waveformcloser to the sine wave. Therefore, the current ripple is reduced moreas compared with the conventional technology, thus achieving torqueripple reduction and efficiency increase. Furthermore, a CPU thatcalculates an output voltage command only needs to add a function ofcalculating a plurality of output voltage command values in which onlyphase advances, and by previously setting the timing of updating avoltage command in a semiconductor integrated circuit, update of thevoltage command a plurality of times can be executed without performanceof processes in the CPU. Therefore, the processing load on the CPU canbe reduced, thus, there is no need to use an expensive CPU.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram of the comparison between a changing waveform of anoutput voltage command that is actually desired to be output and achanging waveform of an output voltage command that is actually output;

FIG. 2 is a diagram of the comparison between an output voltage waveformand a sine waveform;

FIG. 3 is a block diagram of the configuration of an

(3) The whole claim 4 is amended to

“An inverter device comprising:

an output-voltage calculating unit that calculates an output voltagecommand value based on a frequency command value for driving a motor anda state quantity of the motor, in each calculation period;

a PWM-pattern generating unit that outputs a PWM signal according to theoutput-voltage command value output by the output-voltage calculatingunit; and

a switching unit that switches a direct voltage according to the PWMsignal output by the PWM-pattern generating unit and supplies analternating voltage with a predetermined frequency to the motor, wherein

the output-voltage calculating unit includes

-   -   a function of calculating a plurality of output-voltage command        values when the frequency command value is greater than a        predetermined value, and calculating one output-voltage command        value when it is smaller than the predetermined value.”

(4) Claims 1, 2, 5, and 6 are deleted.

7. Attachments

(1) Specification, page 3 and page 4

(2) Claims, page 14 and page 15

between calculation periods. At this time, if an output frequency islow, the calculation period with respect to the cycle of the sine wavebecomes sufficiently short, which allows the sine wave to be dividedinto fine intervals. Therefore, deviation from the sine wave is smalleven by the linear complement, but if the output frequency is high, thecalculation period becomes comparatively long. Therefore, in theconventional technology, it becomes difficult to approximate a finecurve of the sine wave, which causes the deviation from the sine wave tobecome significant.

The present invention has been achieved in view of the above problems,and it is an object of the present invention to obtain an inverterdevice capable of approaching the waveform of an output voltage closerto a sine wave irrespective of whether output frequency is high or low,as compared with the conventional technology, and of reducing theprocessing load of a CPU that calculates an output voltage command.

DISCLOSURE OF INVENTION

In the present invention, an inverter device includes an output-voltagecalculating unit that calculates an output voltage command value basedon a frequency command value for driving a motor and a state quantity ofthe motor, in each calculation period; a PWM-pattern generating unitthat outputs a PWM signal according to the output-voltage command valueoutput by the output-voltage calculating unit; and a switching unit thatswitches a direct voltage according to the PWM signal output by thePWM-pattern generating unit and supplies an alternating voltage with apredetermined frequency to the motor. The output-voltage calculatingunit includes a function of calculating a larger number ofoutput-voltage command values, when the frequency command value isgreater than a predetermined value, than a case of being smaller thanthe predetermined value.

According to the present invention, the calculation load at a low speedarea can be reduced. Furthermore, a time for calculation only when theoutput frequency is low can be ensured. The calculation includes, forexample, an error correction of an output voltage due to a time forprevention of upper and lower arm short-circuit of the switchingcircuit.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram of the comparison between a changing waveform of anoutput voltage command that is actually desired to be output and achanging waveform of an output voltage command that is actually output;

FIG. 2 is a diagram of the comparison between an output voltage waveformand a sine waveform;

FIG. 3 is a block diagram of the configuration of an inverter deviceaccording to one embodiment of the present invention;

FIG. 4 is a flowchart for explaining the operation of an output voltagecalculator shown in FIG. 3;

FIG. 5 is a time chart for explaining a specific example of operationsfor generating a plurality of output voltage commands in one calculationperiod in the output voltage calculator shown in FIG. 3;

FIG. 6 is a time chart for explaining the operations of a PWM patterngenerator (ASIC) shown in FIG. 3; and

FIG. 7 is a waveform diagram of the comparison between an output voltageobtained by the inverter device shown in FIG. 3 and an output voltagebased on the conventional

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 7. An inverter device comprising: a calculating unitconfigured to calculate at least one output-voltage command value basedon a frequency command value for driving a motor and a state quantity ofthe motor, in each calculation period; a signal output unit configuredto output a pulse-width-modulation signal according to theoutput-voltage command value; and a switching unit configured to switcha direct voltage according to the pulse-width-modulation signal tosupply an alternating voltage having a predetermined frequency to themotor, wherein the calculating unit is configured to calculate aplurality of output-voltage command values when a phase change amount ishigher than a threshold, and to calculate a single output-voltagecommand value when the phase change amount is equal to or less than thethreshold, wherein the calculating unit is configured to calculate morenumber of output-voltage command values when the frequency command valueis higher than a threshold than when the frequency command value islower than the threshold.
 8. An inverter device comprising: acalculating unit configured to calculate at least one output-voltagecommand value based on a frequency command value for driving a motor anda state quantity of the motor, in each calculation period; a signaloutput unit configured to output a pulse-width-modulation signalaccording to the output-voltage command value; and a switching unitconfigured to switch a direct voltage according to thepulse-width-modulation signal to supply an alternating voltage having apredetermined frequency to the motor, wherein the calculating unit isconfigured to calculate a plurality of output-voltage command valueswhen a phase change amount is higher than a threshold, and to calculatea single output-voltage command value when the phase change amount isequal to or less than the threshold, wherein the calculating unit isconfigured to calculate a plurality of output-voltage command valueswhen the frequency command value is higher than a threshold, and tocalculate a single output-voltage command value when the frequencycommand value is lower than the threshold.